The field of this invention relates to semiconductor memory devices utilizing differential data lines for detection and determination of binary data and particularly the elements involved in reading and writing to semiconductor memory devices.
Prior art semiconductor memories utilizing differential data (bit) lines typically involve a column of memory cells between two differential bit lines. Each of the memory cells are coupled to both differential bit lines, and a sense amplifier also coupled to each of the differential bit lines senses the binary state of one of the memory cells in the column of memory cells arranged between the differential bit lines (see for example FIG. 1).
There are typically many columns which are arranged on a semiconductor chip and each of those columns is becoming increasingly filled with more memory cells which are being decreased to take up less chip area. These smaller memory cells store less charge which must create voltage swings on the bit and bit bar lines to be sensed by the sense amplifier. Typically, one memory cell in the entire column of memory cells is selected to be read by applying a read signal on a word line coupled to the particular memory cell. That read signal causes the memory cell to be coupled to both bit lines where the difference in voltage between the two bit lines is compared by the sense amplifier. That difference determines the output from the sense amplifier which represents the binary logic state of he memory cell which was selected and read.
Increasing miniaturization has caused the memory cells to store less charge, which charge must create voltage swings on the differential bit lines. Moreover, larger arrays have increased the parasitic capacitance (particularly the capacitance caused by the long bit lines insulated from the semiconductor substrate) of the bit lines such that more time is required to charge and discharge the parasitic capacitive loads by the smaller memory cells which store less charge.
A prior art solution to this problem involves precharging the bit lines to a particular value, which is usually intermediate between the voltage levels which represent the extremes of the binary logic states. Thus, for example, if the extreme high for representing a binary one is 5 volts and the extreme low for representing a binary zero is 0 volts, precharging of the bit lines would apply 21/2 volts on each bit line so that a particular memory cell would have to drive each of the differential bit lines only 21/2 volts in the appropriate direction.
One particular form of prior art involves the use of a recovery pulse prior to the actual reading of the memory cell device. The recovery pulse does not occur during the reading of the memory cell. Such a prior art device is shown in FIG. 1, where a portion of a semiconductor memory is shown. The memory includes a plurality of memory cells 21 which store binary data. The memory cells are arranged in columns, there being two columns of memory cells shown in FIG. 1. A pair of differential bit lines, arranged as two columns, surround each column of memory cells. Thus, one differential bit line 22 (bit) is associated with its inverse, the other differential bit line (bit bar) 23. Each memory cell 21 has a first output 12 and a second output 13 which couple the memory cell between the differential bit lines to provide signals which correspond to the binary data stored in the memory cell when reading that memory cell. Of course, these lines 12 and 13 provide the signals corresponding to a binary state when writing to the memory cell. A sense amplifier 11, having differential inputs, as is well known in the art, is also coupled between each pair of differential bit lines. Word line 27 and word line 28, arranged as rows, are coupled to the memory cells as shown in FIG. 1. Thus, for example, word line 28 is coupled to each memory cell 21 which is coupled via outputs 12 and 13, to bit line 22 and bit bar 23. A read/write clock means is usually coupled to the word lines to supply a read or write signal over the word line to the memory cell to permit the memory cell to be written to or be read from.
Also coupled between the pair of differential bit lines is an MOS field effect device M20, shown in FIG. 1, the gate of which is coupled to a clock 1 (CLK 1) signal; this field effect device serves to equalize the differential bit lines during a recovery pulse which occurs prior to the actual reading of the memory cell. A typical sequence of this prior art memory, shown in FIG. 1, will be described illustrating the recovery pulse. Assume a read cycle (for reading the lower left cell 21 between lines 22 and 23) is ending where the bit line 22 is high at substantially 5 volts and the bit bar line 23 is low at substantially 0 volts. Prior to the next reading of memory cell 21, the recovery pulse occurs by applying the clock signal CLK 1 to the gate of M20 which is coupled to a clock which provides a signal CLK 1. In the embodiment shown in FIG. 1, CLK 1 provides a high signal (e.g. 5 volts) during thc recovery pulse which causes M20 to conduct allowing a current path to develop between the pair of differential bit lines which causes those pair of differential bit lines to be equalized at approximately the same voltage. In this particular instance, the CLK 1 clock pulse causes the pair of differential bit lines to be equalized at a voltage which may be 21/2 volts, which is intermediate between the extremes of the voltage ranges allocated to the binary data. The recovery pulse lasts for a certain period of time, which time is designed to assure that the pair of differential bit lines will be substantially equalized at the end of the recovery pulse. For this purpose, the gate width of devices such as M20 are typically large to permit considerable current flow. Following the recovery pulse, a memory cell is selected for reading by asserting the appropriate word line. Thus, for example, a read signal is applied to word line 28 causing memory cells 21 in both columns shown in FIG. 1 to be activated for reading by the sense amplifiers 11. The memory cells 21 produce their output at outputs 12 and 13; the output from the lower left cell 21 between lines 22 and 23 drives, in this particular example, bit line 22 high (to about 5 volts) and bit bar line 23 low to about 0 volts.
It can be seen that even with the recovery pulses, large voltage swings occur on the differential bit lines. Because of the parasitic capacitance loads and the small memory cells, time is required for those differential bit lines to be driven through those large voltage swings. Without the use of a recovery pulse or a precharging of the differential bit lines, even larger voltage swings occur on the differential bit lines requiring more time to charge and discharge parasitic capacitive loads. Whether or not the recovery pulse is used, the large voltage swings cause power spikes on the power supply lines, such as Vcc which is usually a power supply voltage (e.g. 5 volts) as well as Vss, a second power supply which is often ground. The voltages described herein are usually with respect to ground. Moreover, positive (5 volt) logic is described throughout.
It is an object of the invention to keep the analog voltage swings on the differential bit lines in memory devices small while performing a read operation. Moreover, it is an object of the present inventiOn to avoid the power spikes occurring on the power supply lines caused the the large voltage supply swings. Moreover, it is an object of this invention to provide semiconductor memory devices having faster access time when reading the memory devices.